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| SSM60T03GP,S N-channel Enhancement-mode Power MOSFET Low gate-charge Simple drive requirement Fast switching Pb-free, RoHS compliant. D BV DSS R DS(ON) ID 30V 12m 45A G S DESCRIPTION The SSM60T03GS is in a TO-263 package, which is widely used for commercial and industrial surface-mount applications. This device is suitable for low-voltage applications such as DC/DC converters. The through-hole version, the SSM60T03GP in TO-220, is available for vertical-mounting, where a small footprint is required on the board, and/or an external heatsink is to be attached. These devices are manufactured with an advanced process, permitting operation up to a maximum junction temperature of 175C. G DS TO-263 (S) G ABSOLUTE MAXIMUM RATINGS Symbol VDS VGS ID @ TC=25C ID @ TC=100C IDM PD @ TC=25C Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1 D TO-220(P) S Units V V A A A W W/C Rating 30 20 45 32 120 44 0.352 Total Power Dissipation Linear Derating Factor TSTG TJ Storage Temperature Range Operating Junction Temperature Range -55 to 175 -55 to 175 C C THERMAL DATA Symbol RJC RJA Parameter Maximum Thermal Resistance Junction-case Maximum Thermal Resistance Junction-ambient Value 3.4 62 Units C/W C/W 9/16/2005 Rev.3.1 www.SiliconStandard.com 1 of 5 SSM60T03GP,S ELECTRICAL CHARACTERISTICS (at Tj=25C, unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=250uA Min. 30 1 Typ. 0.03 25 11.6 3.9 7 8.8 57.5 18.5 6.4 200 135 Max. Units 12 25 3 1 250 100 19 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BV DSS/ Tj RDS(ON) Breakdown Voltage Temperature Coefficient Reference to 25C, ID=1mA Static Drain-Source On-Resistance2 VGS=10V, ID=20A VGS=4.5V, ID=15A VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance 2 o VDS=VGS, ID=250uA VDS=10V, ID=10A VDS=30V, VGS=0V VDS=24V ,VGS=0V VGS= 20V ID=20A VDS=24V VGS=4.5V VDS=15V ID=20A RG=3.3 , VGS=10V RD=0.75 VGS=0V VDS=25V f=1.0MHz o Drain-Source Leakage Current (T j=25 C) Drain-Source Leakage Current (T j=175 C) Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 1135 1816 Source-Drain Diode Symbol VSD trr Qrr Parameter Forward On Voltage 2 2 Test Conditions IS=45A, VGS=0V IS=20A, VGS=0V, dI/dt=100A/s Min. - Typ. 23.3 16 Max. Units 1.3 V ns nC Reverse Recovery Time Reverse Recovery Charge Notes: 1.Pulse width limited by safe operating area. 2.Pulse width <300us, duty cycle <2%. 9/16/2005 Rev.3.1 www.SiliconStandard.com 2 of 5 SSM60T03GP,S 125 90 100 T C =25 o C 10V 8.0V ID , Drain Current (A) T C =175 C o 10V 8.0V 6.0V ID , Drain Current (A) 6.0V 75 60 5.0V 30 5.0V 50 25 V G =4.0V V G =4.0V 0 0 0 1 2 3 4 0 1 2 3 4 5 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 80 2 I D =15A T C =25 C 60 1.6 I D =20A V G =10V Normalized R DS(ON) RDS(ON) (m ) 40 1.2 20 0.8 0 2 4 6 8 10 0.4 -50 25 100 175 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( o C) Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 3 100 10 2 1 VGS(th) (V) 1 0 1.5 -50 T j =175 C IS(A) o T j =25 C o 0.1 0 0.5 1 25 100 175 V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( C ) o Fig 5. Forward Characteristic of Reverse Diode 9/16/2005 Rev.3.1 Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 3 of 5 SSM60T03GP,S f=1.0MHz 12 10000 I D =20A VGS , Gate to Source Voltage (V) 9 C (pF) V DS =16V V DS =20V V DS =24V C iss 6 1000 3 C oss C rss 0 0 6 12 18 24 100 1 8 15 22 29 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 1000 1 Normalized Thermal Response (Rthjc) Duty factor = 0.5 100 0.2 0.1 ID (A) 100us 10 0.1 0.05 PDM 0.02 t T Duty Factor = t/T Peak Tj = PDM x Rthjc + T C 1ms 10ms 100ms DC 0.01 Single Pulse 1 0.1 1 10 100 0.01 0.00001 0.0001 0.001 0.01 0.1 1 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG 4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform Fig 12. Gate Charge Waveform 9/16/2005 Rev.3.1 www.SiliconStandard.com 4 of 5 SSM60T03GP,S Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 9/16/2005 Rev.3.1 www.SiliconStandard.com 5 of 5 |
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